Here, we answer everyone's favorite questions about Analog Rails. Enjoy!

• Q: Automate analog layouts. We have precise signals! How are you going to do that?

• A: We challenge your layout designer on routing. Our router is electrically and differentially aware. Even our automatic placement is router aware.

• Q: You are using built in Pcells?

• A: Yes. Our pcells are formulaic and based on the cell based design rules. The layout editor and router work with these structures to make automation easy. For FETS, we handle the AD, AS, PD, PS, SA, SB, SC of the actual layout AT ALL TIMES based on abutment. We also have automatic differential pcells. It creates a common centroid differential structure with a symmetrical guard ring and gate protection diodes. You think you have an advantage with YOUR pcells? YOU DON'T. Our pcells are created with tool knowledge based on manual editing, automatic placement, and automatic routing. They consist of layers and distances that are are a function of spacing, enclosures, extensions, etc.

• Q: How about parasitic capacitance and wire matching?

• A: We have it, along with selected R extraction. Matched nets run together with a shield around them.

• Q: Why do you include density fill?

• A: We want the differential routes and devices to see identical tiling.

• Q: Can your tool work with our current flows and methodologies?

• A: We are OA based, so you can plug and play with Cadence. As far as your present methodologies, let's face it, when was the last time you taped out in time? You are always late getting out, and you always cut corners at the end on your verification process. An automated, correct by construction flow is what you should be doing, not a flow based on waiting, verification, and troubleshooting. No more duct tape, staples, retrofitting, etc. Ever hear the expression "measure twice, cut once"? Setup the measures properly, then hit the O (optimization), P (autoplacement), and R (autorouting) buttons and simulate the final placements. If you think you can improve what we did, you can edit in our tool, or any other Open Access based system.

• Q: Can you automate the creation of a cyclic A/D?

• A: Analog is our first name. What do you think? Amplifiers, fringecaps, switches, digital, etc. The entire multiple hierarchy block...and more.

• Q: Are you suggesting that our engineers do their own layouts?

• A: Yes. Layout is now fun. Just press "P", snap devices around if you want to change the locations. The designer can now update the schematic with new W's to stay further from triode, since doing their own layouts show free space immediately. Then auto route and simulate with the 3D wire and device parasitics. FYI: Our automatic router is preroute aware, just in case you want to control some of the routes yourself.

• Q: Digital place and route? I thought you just did analog automation.

• A: Not only are there lots of analog content in analog blocks encoders, decoders, phase generators, etc, but precision analog (for example, above 10 bits ADCs, precision references, etc.) usually requires calibration where a digital code is used to multiplex in currents or parallel devices. The analog designer can now run digital place and route with a touch of a button. Standard cell layouts are not needed. We generate them on the fly and pack them in better then anybody. The connectivity, cross-probing, etc are all synchronized with the schematic.

• Q: Why not use the supplied standard cells layouts?

• A: Because they aren't created with our router mind. For us, it is all about routing. Don't worry, we will guarantee setup and hold times.

• Q: Do you have simulators?

• A: We support all Hspice compatible simulators. We ship with Msim and Gnucapplus. View the waveforms in our waveform tool. Measurements, voltages, currents, and operating points (vod, vds-vdsat) are backannotated onto the schematics at any time point and corner. Click the waveform, and see the values update in the schematic.

• Q: Where is the full layout automation demo?

• A: Sorry, but we aren't going to show our competitors how to do it. You will need us to show you on-site.

• Q: How do you set matching?

• A: It is automatically done if you run the automatic placer, or you can do it manually by hitting "=" and the pair of devices to interdigitize, or hitting the clone icon, then matching devices/blocks. Ridiculously simple.

• Q: How many levels of hierarchy can you handle at a time?

• A: All levels. We now have a full chip flow.

• Q: How do you size the wires?

• A: Our simulation environment feeds the router. We use Kirchoff's laws that were established in 1845. Isn't having an integrated flow nice?

• Q: What about electromigration (EM) and IR drop?

• A: For EM: User selects "%". All route segments and vias exceeding that show up in layout. For R, I, and V: Just select 2 points in the layout.

• Q: Do you support GDSII?

• A: We save to OpenAccess and have a gui that outputs to GDSII

• Q: How do you compare with Cadence?

• A: It is like comparing a shovel with a bulldozer. Our tool is automatic. Enter the topology and test-bench. We will auto-match, auto-size, place, and route. No scripts or PCell code required. We read in the technology rules and automate the entire process. How many people do you know who create their layouts automatically with Cadence? Even in our manual mode, Analog Rails is more powerful than Virtuoso, because Virtuoso is a drawing program. It relies on error checking tools once the layout is done. Users may as well use Photoshop and convert the format and run the same checkers. Using parasitic estimations rather than using the real layouts is a mistake in 90n and below.

  1. We don't allow violations to occur in the first place.
  2. Your simulation results will always have the real parasitic values because layout is done in minutes.

  Do you use the built-in fonts from Microsoft Word, or do you have a team of people customizing it? Why isn't the automation built into the tool? Do you really think your Data Converter group is different than your competitors? C'mon, get over it. You ain't any different. We know what you want. If you don't trust us, run Calibre when you are done. We have a great interface to our tool that zooms into any error that you may find.

• Q: Are you complimentary to Virtuoso?

• A: We read the same database (Open Access), so you can use both platforms at the same time. Use Analog Rails for creation. Use Cadence, Synopsys, Mentor, 3rd-party point tools, or Analog Rails for verification. We produce extracted views to allow the user to verify from anywhere.

• Q: I just want to work on the schematic. Will Mr. Fixit readjust the layout?

• A: We allow the user to decouple the layout. The user can decide to synchronize the schematic and layout. Mr. Checkit, Mr. Fixit, and Mr. Nudgit will update the layout. Once done, the layout will update the schematic with parasitic info from the layout instantly ( SA, SB, AD, AS, PD, and PS, etc). The user can also keep the sync on for constant 2-way communications. Same with dummy devices. Add them to the layout with a mouse click, and they appear in the schematic. They share the same database.

• Q: What happens to the layout if I change my schematic?

• A: You may only change the preroute in "railed" mode. Changes will automatically ripple throughout the layout, forcing compliance to the design rules. Once your are happy with your changes, either auto-route, or place and route.

• Q: Why do we need layout on the fly?

• A: For simulation accuracy. At feature sizes below 130n, SA and SB have a large effect. The bogus pre-layout calculations that are provided in cdf/pcalls are no longer going to cut it.

• Q: Why all the emphasis on simulation, I thought you were a layout tool company?

• A: Neither simulation nor layout can ultimately be done right without also doing the other, so we seamlessly integrate both into our tool.

• Q: Can you handle 40n and other new processes?

• A: That is our speciality.

• Q: You expect me to believe this is really "correct by construction?"

• A: http://www.correctbyconstruction.com... see?

• Q: Can you give me more specifics about your automatic placer?

• A: It is router-aware, since our router developers built it. Although we expect the placement will be good, the user can manually adjust the placement with its auto snap, abutment, and repel, then launch the router. we offer many floorplans to choose from with different aspect ratios.

• Q: How about manual routing?

• A: Very powerful. Connectivity and DRC rule aware, collision avoidance, automatic maximum via insertion. Terminals light up during routing to show possible end points. Thicken wires a pitch at a time with a mouse click.

• Q: And the automatic router?

• A: Correct by Construction™. DRC/LVS correct, automatic well tap connection, gate protection diode option, double via option. Differential routes shielded. Single-ended shielded routing option (set in schematic). Maximum wire length and area per layer. We handle the new design rules down to 28n.

• Q: Is your optimizer difficult to use?

• A: Not ours. It is completely integrated into the schematic. Click onto the checkbox next to the property, match the devices, place the predefined measures into the schematic, use our testbench templates or build your own, then launch. We have 2 global and 2 local algorithms to pick from. Comes with free support.

• Q: How about differential signals/layouts?

• A: You specify the type of differential structure in the schematic and we generate and route it differentially with dummy extensions and sidewall shields. With analog as our first name, you better believe we can do this.

• Q: What if we don't want the shield for differential routes?

• A: Then delete them after the router completes.

• Q: Do you have a constraint manager?

• A: Since we specialize in analog, we need to handle constraints, but you are not going to believe how easy it is to set them. There are far fewer constraints to setup than in competing products. We have a strong grasp of the obvious. "No brainer" constraints are built in. We make opinionated software, and we are biased towards the conservative side, so real estate savings is a lower priority than circuit performance. That being said, layouts can be smaller with our approach since you can be more aggressive on layout sizes because your simulations have taken the real layout values into account.

• Q: How do I make PCells and Netlisting procedures?

• A: FET, resistor, moscaps, and fringecap, diodes, bipolars, and mimcap PCells are all automatic. The only pcell we do not handle are inductors. We handle layout cells of those. It is rare to see linearly scaling inductors, so you would just instantiate the layout views of those. No code writing required. The differential structures are automatically handled. Properties and netlisting procedures use intuitive text file and GUIs.

• Q: But our PCells and CDF's are modeled perfectly.

• A: You think so? We don't. We extract the values from the layout, not bull&%$# callbacks.

• Q: I want this now! Gimme Gimme!

• A: Contact us via our contact link. Discussions must involve a SENIOR CIRCUIT DESIGNER.

• Q: Analog Rails? What's with the "Rails?"

• A: The "Rails" represents a framework to create integrated circuits quickly. No steering needed. We know the direction you want to go in.

• Q: What is your sales strategy?

• A: Make a product that is 10x better than the competition. Build it and they will come.

• Q: How can 35 people compete with thousands?

• A: We have developers. They have meeting goers.

• Q: What cheap labor area do you export your work to?

• A: We off-loaded work from Scottsdale to Chandler to take advantage of the cheaper labor rates.

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