Here, we answer everyone's favorite questions about Analog Rails. Enjoy!
- Q: What is Analog Rails?
A: Analog Rails is a COMPLETE mixed signal OPEN ACCESS BASED EDA PLATFORM that allows the circuit designer to be a "One Stop Shop". NO CAD OR LAYOUT GROUPS NEEDED. Even design management is included. It combines automatation (front to back), correct by construction manual editing, and verification that allows mixed signal designs to be designed from scratch or migrated in minutes rather than months.
- Q: I never heard of Analog Rails. Are you a startup company?
A: No. We are an upstart company. We have been at this for 9 years, and we are releasing our 3rd complete overhaul on May 16th. Since customization is not required, your CAD group has probably not informed you. They prefer to hack and patch up 15 year old software that was never intended to be made for automation.
- Q: Can our layout designers use Analog Rails?
A: No. This is a circuit designers tool. The circuit designers should do their own layouts. Automation of layout structures and routes allow simulation with all parasitics at all times. The circuit designers create better layouts by utilizing black space and making tradeoffs that the layout designer cannot make. Automation enables "what if" scenarios. Our automatic router is DRC/LVS correct and ELECTRICALLY AWARE. The layout designer has no chance against our automation coupled with the circuit designer.
- Q: How much CAD support is needed?
A: None. Analog Rails is a complete flow that includes design/data management and a "So Easy, An Analog Circuit Designer Can Do It" PDK interface. Customer can easily control the netlisting procedures and measurements/calculators for in-house simulators. The data management system works with SVN, GIT, and Perforce. We can add more. It is trivial. Our design management system, unlike 3rd party DM systems, shows what has changed in the designs and the PDK.
Q: I noticed you have digital place and route? I thought you just had analog automation.
A: Run digital place and route with a touch of a button, all within the Analog Rails design environment. Just like in analog mode, full cross probing and synchronization with the schematic is maintained. Your standard cells are converted to characterized and parameterized standard cells on the fly. Currently, the digital place and route is not timing based. Timing based synthesis will be released in 2013-Q4.
Q: How do we make pcells that will work in our process?
A: With our "So Easy, An Analog Circuit Designer Can Do It" PDK interface. The proper STI layout effects will be netlisted out AT ALL TIMES based on abutment, well distances, diffusion group distances, etc. No more bull &*%$ callbacks. The common centroid differential structures with a symmetrical guard ring and gate protection diodes are automatically generated. The structures are created with tool knowledge based on manual editing, automatic placement, and automatic routing. For non-standard structures, the library group can create pcells graphically. Coding is not needed.
Q: How do you set matching?
A: Press "=" and the pair of devices to interdigitize. Simple. The differential router creates a shielded wall.
Q: How do we customize?
A: Hearing the complaints that Analog Rails has taken the “creativity away from the analog circuit designer”, advanced customization features have been added for engineers who get paid by the hour, or the religious engineer who really believes that only they have mastered true symmetry.
Q: How to you handle high speed signals?
A: Tag nets as "RF", to leave plenty of space in the route. Tag the FET as RF to reduce the met1 on the drain.
Q: How to you see electromigration (EM) and IR drop?
A: For EM: User selects "%". All route segments and vias exceeding that show up in layout. For R, I, and V: Just select 2 points in the layout.
Q: Is there an "ECO" mode? Can we decouple the layout?
A: Yes and Yes. The user can synchronize, unsynchronize, and even put the layout in "derailed" mode. The user can also make manual modifications after the router completes, then can optionally rerun that router to finish uncompleted routes. We are always LVS aware.
Q: Why do we need layout on the fly?
A: For simulation accuracy. At feature sizes below 130n, SA and SB have a large effect. The bogus pre-layout calculations that are provided in cdf/pcalls are no longer going to cut it. There is no reason for the circuit designer to wait several days/weeks for the layout to get done to get the parasitics.
Q: Can you handle 22n and other new processes?
A: We are working on double patterning and expect to complete next quarter (2013-Q3).
Q: You expect me to believe this is really "correct by construction?"
A: http://www.correctbyconstruction.com... see?
Q: How about manual routing?
A: Very powerful. Connectivity and DRC rule aware, collision avoidance, automatic maximum via insertion. Terminals light up during routing to show possible end points. Thicken wires a pitch at a time with a mouse click. More powerful than Virtuoso.
Q: And the automatic router?
A: Correct by Construction™. DRC/LVS correct. Minimizes capacitance. User setable RF, differential, shielded nets, power mesh, differential and signal aware density fill, automatic well tap connection, double via option. Differential routes shielded. Single-ended shielded routing option (set in schematic). Maximum wire length and area per layer. We handle the new design rules down to 22n.
Q: Is your optimizer difficult to use?
A: Not ours. The simulation environment was built with the optimizer in mind. Place the predefined or custom measurements into the schematic, use our testbench templates or build your own, then launch. Optimizer over all corners and all analysis at the same time. We have 2 global and 2 local optimizers. User can force minimum Vds-Vdsat, Vod, etc.
Q: Can we just buy the pieces we need?
A: No. The flow stays together, which consists of schematic, simulation environment, simulators (unlimited), optimizer, layout, analog and digital placers, routers (single ended, RF, differential, power mesh, digital), parasitic extractor, migrator, mimic layout, compactor, nudger, design/data management, and PDK GUI. They play nicely together. The whole is worth more than the sum of the parts. Why separate them?
Q: We successfully use Cadence Virtuoso to make chips. Why do we need Analog Rails?
A: Grandma successfully used a washing board... then the washing machine came out. Get your chip out 10x faster, while keeping your IP safe at home. No need to outsource. What will happen to your company when your competitors go with automation?
Q: Are you complimentary to Virtuoso?
A: We read/write based on the same database (Open Access), so you can use both platforms at the same time. We also produce extracted views to allow the user to verify from anywhere. Then again, we don't see a reason to stick with your stale flow. Analog Rails can replace Virtuoso + all of your surrounding infrastructure.
Q: We trust Cadence. After all, didn't they invent the electron?
A: This was a false rumor carried out by the almighty Cadence Marketing group in the 1990's. The electron existed way over 100 years ago, though Cadence may have tried to patent it. As far as trusting Cadence, most of you don't. Most companies use Mentor's Calibre for DRC & LVS. There are a ton of foundry approved simulators. We support all but Spectre.
Q: Analog Rails? What's with the "Rails?"
A: The "Rails" represents a framework to create integrated circuits quickly. No steering needed. We know the direction you want to go in.
Q: Will you be going to DAC?
A:Yes. Booth 1240
Q: What is the price?
A: Our premium tool is roughly 3x the price that you are currently paying for Virtuoso-XL. The basic tool is cheaper than Virtuoso-XL.
Q: What cheap labor area do you export your work to?
A: We off-loaded work from Scottsdale to Reno to take advantage of the cheaper labor rates.
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