F.A.Q. | Analog Rails™ - Correct By Construction™

Here, Cliff answers everyone's favorite questions about Analog Rails. Enjoy!

Q: Automate analog layouts. We have precise signals! How are you going to do that?
A: We challenge your layout designer on routing. We will beat them. Besides, the circuit designer should not be throwing their designs over wall (or to another country with people happy to steal your designs). Our router-aware automatic placement may be just what you need, but the user can quickly edit the layout. We have a, DRC/LVS/connectivity aware editor where the user can manually snap/repel devices, diffusion groups, and blocks prior to running the router.
Q: Can you handle our pcells
A: Yes, we can handle IPL and OA pcells. You can also user our built-in pcells that uses the real layout parasitics at all times. For FETS, we handle the AD, AS, PD, PS, SA, SB, SC of the actual layout at all times based abutment. We also have automatic differential pcells. It creates a common centroid differential structure with a symmetrical guard ring and gate protection diodes.
Q: How about parasitic capacitance and wire matching
A: We have 3D coupling capacitance extraction, along with selected R extraction. Matched nets run together with a shield around them.
Q: Can your tool work with our current flows and methodologies?
A: We are OA based, so you can plug and play with Cadence. As far as your present methodologies, let's face it, when was the last time you taped out in time? You are always late getting out, and you always cut corners at the end on your verification process. An automated, correct by construction flow is what you should be doing, not a flow based on waiting, verification, and troubleshooting. No more duct tape, staples, retrofitting, etc. Ever hear the expression "measure twice, cut once"? Setup the measures properly, then hit the O (optimization), P (autoplacement), and R (autorouting) buttons and simulate the final placements. If you think you can improve what we did, you can edit in our tool, or any other Open Access based system.
Q: Can you automate the creation of a cyclic A/D?
A: Analog is our first name. What do you think? Amplifiers, fringecaps, switches, digital, etc. The entire multiple hierarchy block...and more.
Q: Our CAD group is trying to block you out
A: You are not alone. That is why we only contact senior circuit designers. We will supply direct support to circuit designers. Support comes free with the tool. We have PDK experts and circuit designers (not core incompetency people, but guys who know how to bias amplifiers). The Skill language has created far too many jobs that should never have existed in the first place. Many people call Virtuoso the "Full Custom IC environment". We call our environment an "Analog Expert System"
Q: Are you suggesting that our prima donna's do their own layouts?
A: Yes. Layout is now fun. Just press "P", snap devices around if you want to change the locations. The designer can now update the schematic with new W's to stay further from triode, since doing their own layouts show free space immediately. Then auto route and simulate with the 3D wire and device parasitics. FYI: our manual routing is better than Cadence, for those who like cutting grass with a scissor.
Q: Digital place and route? I thought you just did analog automation.
A: Not only are there lots of analog content in analog blocks encoders, decoders, phase generators, etc, but precision analog (for example, above 10 bits adc's, precision references, etc.) usually requires calibration where a digital code is used to multiplex in currents or parallel devices. The analog designer can now run digital place and route with a touch of a button. Standard cell layouts are not needed. We generate them on the fly and pack them in better then anybody. The connectivity, crossprobing, etc are all syncronized with the schematic.
Q: Why not use the supplied standard cells layouts?
A: Because they aren't created with our router in mind. We generate the sea of fets and handle timing. If we can optimize an amplifier, we can handle digital.
Q: Do you have simulators?
A: We support Hspice, Msim, and gnucap. In fact, Gnucap is fully supported as much as our other tools, and we actively help the open source development of this product. View the waveforms in our waveform tool. Measurements, voltages, currents, and operating points (vod, vds-vdsat) are backannotated onto the schematics at any time point and corner.
Q: Where is the full layout automation demo?
A: Sorry, but we aren't going to show our competitors how to do it. You will need us to show you on-site.
Q: How do you set matching?
A: It is automatically done if you run the automatic placer, or you can do it manually by hitting "=" and the pair of devices to interdigitize, or hitting the clone icon, then matching devices/blocks. Ridiculously simple.
Q: How many levels of hierarchy can you handle at a time?
A: All levels. We now have a full chip flow.
Q: What about electromigration (EM) and IR drop?
A: For EM: User selects "%". All route segments and vias exceeding that show up in layout. For R, I, and V: Just select 2 points in the layout.
Q: Do you support GDSII?
A: We save to OpenAccess and have a gui that outputs to GDSII
Q: How do you compare with Cadence?
A: It is like comparing a pair of scissors with a lawnmower. Our tool is automatic. Enter the topology and test-bench. We will auto-match, auto-size, place, and route. No scripts or PCell code required. We read in the technology rules and automate the entire process. How many people do you know who create their layouts automatically with Cadence? Even in our manual mode, Analog Rails is more powerful than Virtuoso, because Virtuoso is a drawing program. It relies on error checking tools once the layout is done. Users may as well use Photoshop and convert the format and run the same checkers. Using parasitic estimations rather that using the real layouts is a mistake in 90n and below.
1. We don't allow violations to occur in the first place.
2. Your simulation results will always have the real parasitic values because layout is done in minutes.
Stop drinking the Cadence kool-aid. They are in cahoots with CAD groups that look to customize the environment to fit "their" needs. Do you use the built-in fonts from Microsoft Word, or do you have a team of people customizing it? Why isn't the automation built into the tool? Do you really think your Data Converter group is different than your competitors? C'mon, get over it. You ain't any different. We know what you want. If you don't trust us, run Calibre when you are done.
Q: Are you complimentary to Virtuoso?
A: We read the same database (Open Access), so you can use both platforms at the same time. Use Analog Rails for creation. Use Cadence, Synopsys, or Analog Rails for verification. We produce extracted views to allow the user to verify from anywhere.
Q: I just want to work on the schematic. Why is the layout tool always open?
A: They must co-exist. Schematic changes are reflected in the layout instantly, and SA, SB, AD, AS, PD, and PS are reflected back into the schematic instantly. 2-way communications. Same with dummy devices. Add them to the layout with a mouse click, and they appear in the schematic. They share the same database.
Q: What happens to the layout if I change my schematic?
A: You may only change the preroute (don't worry, we always save a copy). Changes will automatically ripple throughout the layout, forcing compliance to the design rules. Once your are happy with your changes, either auto-route, or place and route.
Q: Why do we need layout on the fly?
A: For simulation accuracy. At feature sizes below 100n, SA and SB have a large effect. The bogus pre-layout calculations that are provided in cdf/pcalls are no longer going to cut it.
Q: Why all the emphasis on simulation, I thought you were a layout tool company?
A: Think again. Our expertise is in circuit design and simulation, but we also understand layout.
Q: Can you handle 45n and other new processes?
A: That is our speciality.
Q: You expect me to believe this is really "correct by construction?"
A: http://www.correctbyconstruction.com... see?
Q: Can you give me more specifics about your automatic placer?
A: It is router-aware, since our router developers built it. Although we expect the placement will be good, the user can manually adjust the placement with its auto snap, abutment, and repel, then launch the router.
Q: How about manual routing?
A: Very powerful. Connectivity and DRC rule aware, collision avoidance, automatic maximum via insertion. Terminals light up during routing to show possible end points. Thicken wires a pitch at a time with a mouse click.
Q: And the automatic router?
A: Correct by Construction™. DRC/LVS correct, automatic well tap connection, gate protection diode option, double via option. Differential routes shielded. Single-ended shielded routing option (set in schematic). Maximum wire length and area per layer. We handle the new design rules down to 28n.
Q: Is your optimizer difficult to use?
A: Not ours. It is completely integrated into the schematic. Click onto the checkbox next to the property, match the devices, place the predefined measures into the schematic, use our testbench templetes or build your own, then launch. We have 2 global and 2 local optimizers. Comes with free support.
Q: How about differential signals/layouts?
A: You specify the type of differential structure in the schematic and we generate and route it differentially with dummy extensions and sidewall shields. With analog as our first name, you better believe we can do this.
Q: What if we don't want the shield?
A: Too bad. You are getting the shield. If you want to lower the capacitance, increase the spacing, but you are getting the shield.
Q: Do you have a constraint manager?
A: Since we specialize in analog, we need to handle constraints, but you are not going to believe how easy it is to set them. There are far fewer constraints to setup than in competing products. We have a strong grasp of the obvious. "No brainer" constraints are built in. We make opinionated software, and we are biased towards the conservative side, so real estate savings is a lower priority than circuit performance. That being said, layouts can be smaller with our approach since you can be more aggressive on layout sizes because your simulations have taken the real layout values into account.
Q: Can we just buy the pieces we need?
A: No. The flow stays together, which consists of schematic, simulation environment, simulator (unlimited), optimizer, layout, placer, router, parasitic extractor. They play nicely together. Why separate them?
Q: Can you read Virtuoso Technology files?
A: Yes. We will also set up your process for free. It usually takes a week. We also have an easy GUI to fill in.
Q: How do I make PCells and Netlisting procedures?
A: FET, resistor, moscaps, and fringecap PCells are all automatic. They use design rules. No code writing required. If you want to define you own primitives, including bipolars, inductors, mimcaps, we will read the pcell code, provided that they are written in one of the open standards (not skill). The differential structures are automatically handled. Properties and netlisting procedures are handled in intutive text file and GUIS.
Q: I want this now! Gimme Gimme!
A: Contact us via our contact link. Discussions must involve a SENIOR CIRCUIT DESIGNER.
Q: Analog Rails? What's with the "Rails?"
A: The "Rails" represents a framework to create integrated circuits quickly. No steering needed. We know the direction you want to go in.
Q: What is your sales strategy?
A: Build it and they will come. This isn't like comparing the Betamax versus VHS. This is a power saw versus a handsaw. We believe the best technology wins, especially if it leapfrogs over the competition.
Q: How do you handle support?
A: With analog circuit designers, not EDA guys.
Q: How can 30 people compete with 3000?
A: We have developers. They have meeting goers.
Q: What cheap labor area do you export your work to?
A: We off-loaded work from Scottsdale to Chandler to take advantage of the cheaper labor rates.
Q: Why doesn't the press cover you?
A: Press? Did you mean shills? There is no press. We don't have enough money to pay them off. We run a tight ship.

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