Our mission is to automate the design of systems on a chip (SOC). The goal for non-commodity ICs is to be first to market, and our design environment was created to do just that. Our product name, Analog Rails, was chosen for a reason. The "Rails" refers to a well structured framework, and our niche is automation of circuits with "Analog" and/or RF content. We also have digital place and route, enabling completion of the entire SOC.

For a given topology, we expect the circuit designer to complete an amplifier, soup to nuts in 30 minutes. The layout of a scfilter or ADC should take less than an hour. The user should create a topology, place the provided analysis and measurement components into the schematic, then run the sequence of optimization, automatic placement, manual adjustment (if needed), automatic routing, and parasitic simulation. Simulations will always use the layout extracted values. There is no reason to wait 2 months to get the parasitic values incorporated into the simulation run. We believe our layout automation is so good, the circuit designers will be doing their own layouts. The designs will be better if the circuit designer does them, by tweaking the design based on black space and routing flow. Also, in the time it takes the circuit designer to explain the matching, critical paths, thermal gradients, the circuit designer can complete the layouts on their own.