Simulate layout parasitics at all times

Why wait two months to get layout parasitics from wiring, length of diffusion (STI Stress Effects), and well proximity? Currents can be off by 20% without knowing these layout generated values. Analog Rails uses the layout's extracted values at all times. Now setting reltol has more meaning.

Optimization made easy

Place your measurements and analysis components in our OA based schematic, choose properties to optimize, go to lunch. Return to see the final circuit sized, layout completed, and parasitic extracted simulation results.

3^rd Party simulators supported

We incorporate 3^rd party simulators. Why not? We make no money from simulators, but we need them to complete the flow. We currently support Hspice, Msim, and others. Our netlister is customizable. You can even netlist out Verilog-AMS.

Measurements and analysis components in schematic

Place settling time, overshoot, bandwidth, phase margin, risetime, and etc. components into the schematic, along with multiple analysis components (ac, dc, tran, pss, etc). Corner setups are included in the analysis components.

Simulator included

Run an infinite number of simulations. We fully test and support GNUCap, which will be greatly enhanced this year. A major effort is being put into incorporate Fastspice, RFspice, Harmonic Balance, co-simulation with digital simulators, and an API to make the simulator scriptable and extendable.

Built-In Timing

Digital cells will be optimized in our digital place and route with our built-in timing. This will ensure your signal will reach the latch prior to the clock input over all corners.

Robust Hierarchical/Configuration Editor

Create optimization, simulation, and even layout settings on a block instance basis.

Automatic analog placement and differential pcells

Set automatch on, press the "P" button, and enjoy the show. We know analog, and you can expect to see common centroid structures with guard rings, multiple dummies, and extended wells to reduce the STI stress and well proximity effects. Don't trust our layouts? Our name begins with "anal." We will challenge your layout designers.

Automatic analog routing

Transistor-level router that also handles differential signals, with wire extensions and shields. We will route 100% of the signals and DRC correct. Impossible you say? We will move devices automatically if we cannot route it.

Integrated Floor Planner

Iterate bottom up and top down. Hierarchical editor allows user to change modes. Block level router can provide RC information to lower level blocks. Abstracts on the fly!

Automatic dummy creation

Add a dummy to the end of a diffusion group. The dummy will automatically be added to the schematic with the proper connectivity. Schematics and layouts are always synchronized.

Digital timing based place and route

Standard cell layouts will be automatically generated (we don't need your layouts). We will then place them in the most efficient flow based manner, optimize sizing based on parasitic estimates, route, extract RCs, measure, optimize sizing, route, extract, and continue to cycle through until timing is met.

Manual DRC/LVS correct by construction™ layout

Much more powerful than the competition. PCells and differential PCells built-in. Place mosfets, fringecaps, mimcaps, resistors, bipoloars, etc., no CAD scripts required. PCells snap/repel/permute based on schematic connectivity. Collision avoidance on wiring. Built-in DRC and LVS ensures that it is impossible to have violations. Users can do some manual routing, then let the automatic router finish the job.

Millions of shapes in a second

We did a complete rewrite of our editor this year. It works directly from the OA database and is fast as lightning. We are no longer an analog block creation tool. We are now going to handle the entire chip.