Semi-automatic IC Design Environment
- Unified schematic/layout built from scratch on OA
- OA = Compatible / coexists with Virtuoso
- Ridiculously simple. Install and run in minutes
- No CAD effort needed. Techfiles included, but customizable.
- We thrive on small feature sizes, such as 130n to 45n
Schematic
- OA based: Switch between competitors and Arails
- Controls layout devices and connectivity
- Create layout matching, dynamic/static spacing, etc
- Simulation test-benches built in, saves with schematic
- Accurate simulations: SA, SB, AD, etc. extracted on the fly, even when cell is flattened and merged!
- Dummies automatically added to schematic from layout
- Cross-probes with layout and waveform
Simulation Environment
- Supports most simulators
- Simulate parasitic extracted values AT ALL TIMES
- Multiple simulator, analysis, corners
- Backannotates voltages and currents to schematic
- Digital diagnostics with Veritools (October release)
- Passes wire sizing (EM, IR drop) to router (NEW)
- Free simulator included (gnucap)
Circuit Optimization
- Multiple analysis, testbenches, corners
- User defined measurements
- Over 30 built-in measurements, such as gain & phase margin, overshoot, settling, THD, etc
- Testbench examples: Amp, PLL, VCO, etc
- Click onto parameter to optimize
- Simple results filtration and loading into schematic
- Batches off to multiple machines
Layout
- Always LVS clean, devices and wires align/snap/repel
- Design rules always enforced, at all times
- Differential structures automatically generated
- Schematic driven cloning of groups of devices
- Auto completes wiring
- Changes in schematic automatically adjusts layout
- Add dummies with a single click
- Smash many levels of hierarchy for layout efficiency
PCells
- No scripts needed! All design rule driven
- Exact parasitic info backannotated
- Differential structures and matched wiring
- Contains ring, shields, dummies, gate protection diodes
Autorouter
- Tunable costs
- Differential routing with shields
- Annealing nudges components in layout
- 3x spacing on dynamic nets
- Double vias
- Automatic well tap connections
Autoplacer (October Release)
- Tunable costs
- Differential structures (analog), digital, and blocks
- Router aware
- Multiple placement created
- WPE aware
